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EnCharge AI

Posted 2 months ago

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Physical Design Engineer

BangaloreOn-siteFull-time

AI Summary

Physical Design Engineer handles RTL-to-GDSII flow, floorplanning, placement, CTS, routing, STA, and power/EM/PI checks for advanced-node silicon, with AI/ML automation for design flow.

About this role

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Physical Design Engineer (2-4 Years Experience)
We are looking for a high-caliberPhysical Design Engineer to join our fast-paced startup team. This role is designed for "top 1%" talent—engineers fromtier-1 universities (IIT/NIT/BITS or equivalent) who possess a relentless "go-getter" attitude and the critical thinking skills required to solve complex, next-generation silicon challenges.
If you are eager to move beyond standard digital flows into the future ofAI-driven automation, this is your playground.

Key Responsibilities
  • End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC).
  • Performance Optimization: Execute high-performance design closure focusing onPPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below)
  • Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, andCPPR (Common Path Pessimism Removal) optimization.
  • Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery.
  • Innovation: Develop and integrateAI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time.
Qualifications & Requirements
  • Education: B.Tech/M.Techin Electrical/Electronics Engineering from aTop Tier University.
  • Experience: 2–4 years of hands-on experience in Physical Design within the semiconductor industry.
  • Tool Expertise: Expert-level proficiency in industry-standard tools (PreferredInnovus).
  • Technical Depth: Strong understanding of multi-corner multi-mode (MCMM) closure, low-power design techniques (UPF/CPF), and physical verification.
  • Mindset: A proven "go-getter" who is diligent, detail-oriented, and capable of taking complete ownership of blocks under tight deadlines.
  • The "Plus": Proficiency in Python/Tcl and experience usingAI/ML models for EDA tool automation or predictive PPA analysis.
  • Location: Bangalore

Skills

CPFCPPRCrosstalkCTSDRCEDA Tool AutomationEM AnalysisERCFloorplanningInnovusIR DropLow-power DesignLVSMCMMPlacementPythonRoutingRTL-to-GDSIISignal IntegritySTATCLUPF

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