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E-Space

Posted 5 months ago

Principal DV Engineer

Saratoga, CAOn-siteFull-time

AI Summary

Verifies custom ASICs for satellite and wireless telephony using Verilog, SystemVerilog, and UVM, leading verification efforts through chip tapeout.

About this role

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work.

Requirements

  • HDL & Verification Methodology

    · Expert-level proficiency in Verilog and SystemVerilog

    · Proven experience building UVM verification environments from scratch

    · Deep understanding of verification methodologies and best practices

    Programming & Scripting

    · Proficient in C/C++ coding for verification purposes

    · Strong scripting skills in Perl or Python

    · Ability to write and maintain bash scripts for verification flows

    Verification Planning & Execution

    · Experience writing comprehensive test plans

    · Experience writing and maintaining test suites

    · Ability to debug complex RTL simulations

    · Ability to debug gate-level simulations with SDF back-annotation

    · Ability to assess whether SDF timing violations are benign or require attention

    Leadership

    · Proven track record leading code coverage closure

    · Experience leading design verification efforts through chip tapeout

    • What you bring to this role:

  • 10+ years of design verification experience in the semiconductor industry

    • Skills

    BashC/C++Code Coverage ClosureGate-level SimulationPerlPythonRTL SimulationSDF Back-annotationSystemVerilogTest Plan WritingTest Suite MaintenanceUVMVerilogVHDL

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