Posted 21 days ago
Principal Firmware QA Engineer
AI Summary
Lead Firmware QA Engineer who designs and executes functional, performance, interoperability and stress tests for PCIe and related interfaces, collaborating with silicon, FW, and architecture teams; mentors teammates and drives test automation.
About this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Title: Lead Firmware QA Engineer, Astera Labs, Bengaluru, India.
Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.
Basic Qualifications:
- Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 4 years of experience.
Required Experience:
- Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.
- Estimate work, identify dependencies and develop schedules.
- Responsible for designing and executing functional, performance, interoperability and stress tests.
- Work closely with Silicon team, architecture team, FW development team to understand the design and develop test strategies.
- Responsible for manual and automation testing.
- Strong knowledge of scripting ( Python ) is must.
- Responsible for automation development and manual testing.
- Perform Signal integrity and protocol level validation.
- Closely work with development teams to triage and debug issues.
- Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.
- Experience in PRBS testing, loopback and margining tests.
- Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.
- Experience is PCIe compliance testing is a plus.
- Regularly working with Hyperscale's and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.
- Knowledge in validation of NIC controllers and storage controllers is preferred.
- Requirements management and traceability through software development phases.
- Mentoring and coaching team members to help them excel in their jobs.
- Power user of Git, Jira and Confluence.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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