Posted 63 months ago

Senior DFT Engineer

BangaloreOn-siteFull-time

AI Summary

Senior DFT engineer drives DFT flows for digital designs, collaborates with RTL/PNR teams to ensure testability, and defines test structures, vectors, and debug plans.

About this role

We are looking for an experienced DFT engineer, who is capable of driving the required DFT flows for our digital designs. The ability to work closely with rtl and pnr design team to drive testability is a key feature of this role!

Qualifications

Hands-on expertise with commercial test generation tools for large complex designs

Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST and LBIST

Experience generating test patterns and analyzing and debugging test failures

Experience with RTL simulation, synthesis and back end implementation flows

Experience defining and implementing stuck-at and at-speed techniques

Experience running test compression flow

Experience trading off test options with product performance and schedule requirements

Experience creating and releasing full test programs for device screening

Test optimization

Resolve design and flow issues related to DFT, identify potential solutions, and drive execution

Education and Experience

B.E./B.Tech./M.E./M.Tech in VLSI

Minimum of 5 years of working experience in DFT flow of a product company.

Strong fundamentals in digital ASIC design, experience with ASIC test, DFT, and debug

Detailed Responsibilities and Skills

Define DFT strategy and methodologies

Define test structures, debug structures, test plans

Create test vectors, simulate in various modes

Collaborate with physical design team to close requirements

Validate DFT requirements are being met

Work with designers to increase test coverage, debug observability and flexibility

Verify post-PD designs meet DFT requirements

Knowledge of full DFT flow (test structure insertion, pattern generation, simulation )

Hands-on experience with Cadence Genus, Modus tools,

Should have good understanding of Verilog/VHDL

Exposure to low power techniques

Knowledge of TCL and Python scripting is a must

Skills

ATPGAt-speedBack End ImplementationCadence GenusCadence ModusDesign-for-testabilityDevice ScreeningDFT TechniquesIEEE 1500 StandardJTAGLBISTLogic DiagnosisLow Power TechniquesMBISTPattern GenerationPython ScriptingRTL SimulationScan CompressionSimulation ModesStuck-atSynthesisTCLTestability ObservabilityTest CompressionTest Pattern TranslationTest ProgramsVerilogVHDLYield Learning

Senior DFT Engineer

About this role

Qualifications

Education and Experience

Detailed Responsibilities and Skills

Skills

Explore related jobs

More jobs at Omni Design Technologies

Similar ATPG jobs

Jobs in Bangalore

Browse these categories