Posted 73 months ago

Senior Digital/RTL IC Design Engineer

BangaloreOn-siteFull-time

AI Summary

Senior Digital Design Engineer focusing on RTL and verification for high-performance data converters, including digital control for mixed-signal blocks, timing closure, and P&R flow.

About this role

Senior Digital Design Engineer focusing on the digital datapath of high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R flow for the digital controller for high performance data converters in cutting edge technologies

Qualifications

BS/BE/MS/MTech + 5 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes

Strong foundation in digital design concepts for complex ASICs

Hands on experience with the Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc

Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc)

Familiarity with behavioral Verilog code, including wreals

Ability to write thorough testbenches

Preferred knowledge of Genus, Tempus, Modus and other Cadence tool set used for ASIC design flow

Excellent understanding of SystemVerilog

Knowledge of SystemVerilog assertions preferred

Familiarity with place and route tool flow using Innovus preferred but not mandatory

Basic understanding of digital signal processing – MATLAB understanding preferred

Extensive experience with synthesis flow in nano-meter scale CMOS

Extensive experience with place and route flow interface

Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating

Familiarity with timing closure and static timing analysis tools with the MMMC modes

Experience with scan chain vector generation and verification

Experience with flow automation through scripting – shell scripts, Makefile, Python or similar languages

Familiarity with Cadence Encounter tool flow preferred but not mandatory

Skills

AddersBehavioral VerilogCADENCE EncounterCadence Tool FlowCombinational LogicGenusInnovusMMM C ModesModusMultipliersPlace And RoutePythonRTL DesignScanc Chain Vector GenerationScripting (shell, Python, Makefile)Shell ScriptingState MachinesStatic Timing AnalysisSystemVerilogSystemVerilog AssertionsTempusTestbenchesTiming ClosureVerificationVerilogWreals

Senior Digital/RTL IC Design Engineer

About this role

Qualifications

Skills

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