VLSI Verification Engineer

VLSI Verification Engineer

EROS Technologies was founded with a simple motive of offering the clients exactly what they want, how they want and when they want it. By leveraging for its clients its technological edge and right-sourcing advantage, EROS in a short period of time has grown to become one of the most trusted strategic technology partners. Treating every client as the top priority, we customize our solutions and services to align with the unique needs of each client.

Job Title: VLSI Verification Engineer

Location: Santa Clara, CA

Duration 6 Month Contract

Job description:

Verification engineers – OVM/UVM is Mandatory
CPU subsystem/DDR/Modem verification

Additional Information

All your information will be kept confidential according to EEO guidelines.