Analog Layout Engineer

AustinRemote

AI Summary

Designs physical silicon layouts for high-speed mixed-signal circuits such as SerDes, ADCs, DACs and PLLs, handling floor planning, parasitic and noise control, and DRC/LVS/EM-IR verification on advanced TSMC nodes.

About this role

Job Title : Analog Layout Engineer
Client: Arrow Electronics
Experience Required: 7+ years (Relevant)
Work Location: Austin ,TX (Remote)
Visa: All visa, except H1B transfer
C2C engagements are allowed.

TSMC 4NM (Must Have)

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
Experience at Lower node (N3, N5) is critical for this position.

Skills

ADCAnalog LayoutCommon-centroid LayoutDACDRCEM/IR AnalysisERCESD ProtectionFinFETFloor PlanningGuard RingsLayout-dependent EffectsLVSPLLSerdesTSMC 4nm