Analog Mixed-Signal Layout Intern

Role Overview

We are seeking a motivated Analog Mixed-Signal Layout Intern to assist in the design and layout of high-performance analog and mixed-signal IP blocks. You will work closely with experienced layout and circuit design engineers to translate schematic designs into silicon, gaining hands-on experience with advanced technology nodes and CAD tools.

Key Responsibilities

· Assist in layout design of analog and mixed-signal circuits such as: Current mirrors, differential pairs, op-amps, bandgaps, comparators…

· Perform layout-vs-schematic (LVS), design-rule checks (DRC), and parasitic extraction (PEX) to ensure design quality and manufacturability

· Support floor planning, placement, routing, and matching for analog blocks following layout best practices (symmetry, shielding, guard rings, etc.)

· Work with circuit designers to optimize layout for performance, area, and reliability (minimize mismatch, noise coupling, IR drop).

· Document layout work and contribute to layout review checklists and verification reports.

Qualifications

· Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

· Basic understanding of analog/mixed-signal IC design concepts.

· Familiarity with EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics.

· Basic understanding of matching techniques, layout symmetry, and common centroid structures. Strong analytical and problem-solving skills.

· Eagerness to learn advanced layout methodologies for high-speed and low-noise analog design.

What You’ll Gain

· Exposure to industry-standard AMS design flows and tools.

· Opportunity to study high speed layout techniques.

· Mentorship from experienced Circuit and AM layout engineers.

· Hands-on experience with real design projects leading to tape-out.

Preferred Skills (Nice to Have)

· Experience with version control systems (e.g., Git, Perforce).

· Knowledge of CMOS, FINFET devices structure.

· Familiarity with analog layout techniques and parasitic extraction.