Posted 3 months ago
ASIC design and verification enginner
Belgium, BelgiumRemoteContract
AI Summary
A hardware engineer designs and verifies ASICs, writing block-level specifications, debugging RTL, and using SystemVerilog/UVM in a fully on-site, 6-month contract in Belgium.
About this role
ASIC design and verification enginner
For one of our clients in Belgium, we are looking for a hardware engineer with extensive experience in ASIC design and verification. It is for an initial 6 month contract + extensions, and fully on-site at the client's premises.
Qualifications
- At least 5 years experience of ASIC design & verification
- Block level design and specification writing
- Debugging RTL at the block level
- SystemVerilog and UVM - Fluent English
Skills
ASIC DesignBlock-level SpecificationFluent EnglishRTL DebuggingSystemVerilogUVM
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