Posted 3 months ago
Verification Engineer
EindhovenOn-site
AI Summary
A verification engineer designs and implements verification environments for ASIC/SoC digital projects, using C/C++, SystemVerilog, UVM, VHDL, and Verilog to test and validate hardware functionality on-site in Eindhoven.
About this role
Verification Engineer
For a client based in Eindhoven we have opportunities for digital verification engineers for ASIC/SoC.
Skills required for the position:
- 3+ years experience in verification for semiconductors
- C/C++ knowledge
- SystemVerilog
- UVM
- VHDL; Verilog
The role is an on-site freelance contract with an initial length of 6 months.
If you are interested and available shortly, please apply with an updated CV, and we will get in touch shortly.
Skills
C/C++Semiconductor VerificationSystemVerilogUVMVerilogVHDL
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