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Baidu USA

Posted 46 months ago

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CPU Digital Design Engineer

Sunnyvale, CAOn-siteFull-time

AI Summary

Design and integrate a RISC-based CPU subsystem for a cellular modem, focusing on high performance, low power, and small area across multi-nation teams.

About this role

Job Description:
Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in:
- Perform CPU development and design integration for CPU subsystem.
- Micro-architecture and design of RISC based CPU.
- Explore latest technologies in processor for 5G application.

Minimum Qualifications:
- Master Degree in Electrical Engineering, Computer Science or Computer Engineering.
- At least 3 years of CPU related Architect/RTL/Verification/Implementation design experience
- Knowledge and practical experience with common RISC CPU architecture.
- Ability to bring design concept to successful silicon

Preferred Qualifications:
- PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS.
- 5+ years of CPU related Architect/RTL/Verification/Implementation design experience
- Familiarity with CPU architecture knowledge and micro-architecture knowledge
- Familiarity with chip digital design flow, including RTL integration, simulation, STA, clock tree, or low power design
- Familiarity with Symmetric Multi-threading (SMT), ARM/MIPS CPUs, or RISC-V.
- Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture.
- Cross-site working experience is a PLUS.
- Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.

#LI-DNI

Skills

Arm CPUsClock Tree DesignCPU Micro-architectureCPU Subsystem IntegrationDC/EMC Related Timing ConstraintsDigital Design FlowDVTFoundryFPGAImplementation DesignLow-power DesignMIPS CPUsPost-siliconRISC CPU ArchitectureRISC-VRTL DesignRTL IntegrationSLT DebuggingSMP (symmetric Multiprocessing)SMT (symmetric Multi-threading)STA (Static Timing Analysis)Verification

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