CPU Systems Software Engineer
AI Summary
A System On Chip Engineer develops and debugs System-on-Chip designs using Chisel and Chipyard, collaborates with hardware engineers to optimize frequency, area, and power, and profiles microarchitecture bottlenecks.
About this role
System On Chip Engineer
Are you passionate about software, and eager to expand into hardware? Do you love statically typed languages and functional programming? Haskell, Rust, Scala? If you're interested in learning how hardware works, particularly the intricate details of CPU design, this position could be perfect for you.
About the role
Hardware is a vast subject with many expert domains. This position is primarily about behavioural logic with an infinite propagation speed model, also known as digital logic design. Digital logic design separates the concern of correct operation from physical concerns, like frequency, area, power, and layout. This makes digital logic design perfect for software engineers when working in collaboration with hardware engineers who concern themselves with these issues.
The work will largely be in Chisel, and you will be using frameworks like Chipyard. In addition, you will be working with OpenROAD for architectural exploration, and you will learn to interpret reports for power, area, and performance, which will be crucial for architectural exploration. You will learn to read Verilog, which is the de facto interchange format between tools and hardware.
It is not the execution time or memory requirements of the Chisel that is critical, it is that quality of the the Verilog that is generated when Chisel runs(elaboration) that matters. This allows focusing on quality, elegance and clarity of expressing ideas in Chisel, rather than worrying about whether some functional programming concept doesn't run quite as fast as it would have in C++.
Key Responsibilities
- Develop Chisel and Chipyard code, and debug System-on-Chip using simulation and FireSim as well as internal Ascenium tools.
- Profile the system to identify bottlenecks in the microarchitecture.
- Examine existing RISC-V implementations for A/B comparison with Ascenium's technology.
- Collaborate with hardware engineers to identify bottlenecks in terms of frequency, area, and power and to implement solutions in the Chisel code.
- We are using many open source projects, and there will be opportunities to collaborate with, and to contribute to the open source community to help build your open source portfolio
Personal development
Making a CPU is a "target rich environment." In this environment you will find many opportunities to develop your skills, and to expand your areas of interest, for example move deeper into physical considerations, the CPU core, system concerns, and software integration.
At Ascenium, we have a flat hierarchy, and we encourage engineers to participate in non-engineering business interests, such as work culture, procedures, management, recruitment, and technical evangelism.
Why Join Us?
For more information about why people like to work here, see: https://www.ascenium.com/careers.
Skills
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