Formal Verification Engineer - Professional Level
HybridFull-time
AI Summary
A formal verification engineer owns end-to-end delivery on non-trivial RTL blocks, defining verification strategy, writing clean SVA, using formal tools to close proofs, and handing over trusted sign-off artifacts.
About this role
Your mission
You own a defined formal deliverable end‑to‑end (days to a few weeks). You work independently in known contexts, drive proof closure, and hand over sign‑off artifacts that customers trust.
- Own a block/area: clarify requirements, co-define the verification strategy (scope, risks, approach), execute, and close.
- Produce maintainable SVA and a clean formal environment (constraints/assumptions with good hygiene).
- Debug efficiently, partner with designers on fixes, and prevent regressions.
- Keep stakeholders aligned with crisp updates and decision-ready evidence.
Your profile
- Proven experience delivering formal results on non‑trivial RTL (e.g., caches, pipelined processors, DMAs, NoCs).
- Strong SVA skills and hands-on formal tool experience (e.g.: Jasper, VCF, Questa Formal/Onespin).
- Reliable end‑to‑end ownership in a defined scope.
What success looks like in your first ~90 days
- You nail our onboarding bootcamp and earn the team’s trust: you apply the LUBIS way of working and consistently ship clean, reviewable outputs.
- You engage confidently in scoping and planning with the team: you clarify open questions early, surface risks, and help translate scope into a concrete plan.
- You own a deliverable end‑to‑end in a defined area and ship it without a “rescuer”.
Where this leads
The natural next step is our Senior Formal Verification Engineer role — leading customer engagements, owning formal architecture decisions, mentoring Associates and Professionals, and shaping how LUBIS approaches new verification problems. We make that path concrete: review cycles, customer-lead rotations, and clear competency milestones.
Why us?
Skills
AssertionsFormal Proof ClosureJasperOnespinQuesta FormalRTL VerificationSVASystemVerilogVCF
