Jobless Developer

Multimedia Verification

San DiegoOn-siteContract

AI Summary

Contract role designing and verifying multimedia IP for government software integration; responsible for test planning, debugging, adversarial testing, and verification of video codecs and camera/graphics hardware interfaces.

About this role

Multimedia Verification

22nd Century Technologies .. We are Government Software integrators working with DoD and civilian space and are fast growing company in DoD sector with clients like US Air Force, US Navy and Army.

Find more about us at www.tscti.com .


22nd Century Technologies is an equal opportunity employer and considers qualified applicants for employment without regard to race, gender, age, color, religion, disability, veterans status, sexual orientation, or any other protected factor.


Title: Sourcing Req - Multimedia Verification

Location: California - San Diego

Duration: 12 Months


Job Description:

Design Verification of Multimedia IPs.

Minimum Qualification

  • Strong verification skills: test planning, problem solving, debug, adversarial testing.
  • Multimedia video (MPEG-2/4, H.264, VP6/7/8, DIVX & VC1) Camera or graphics (OPEN-GL/CL, DX-9/10/11) hardware experience is preferred.
  • Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C.
  • Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience and/or very strong OOPs programming experience is also a plus.
  • Experience with simulation acceleration tool like Veloce/Palladium is a plus. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting.

Education

Bachelor's Degree Required. Master's Preferred, BS EE/CE/CS required with equivalent experience required.

Qualifications

  • Design Verification of Multimedia IPs.Design Verification of Multimedia IPs.
  • MUST have a background in Multimedia

Additional Information

Thanks & Regards

Aditika Sithta

Technical Recruiter

Phone:908-765-0002 Extn:-261

Skills

C/C++DirectX 10DirectX 11DirectX 9DIVXE-SpecmanH.264MPEG-2MPEG-4OpenCLOpenGLOVMPalladiumPerlRTL DesignRVMShell ScriptingSimulation AccelerationSystem-CSystem VerilogTCLUVMVC1VeloceVeraVerilogVHDLVMMVP6VP7VP8

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