Posted 1 month ago
Photonic Layout Engineer - New Grad
AI Summary
Generates and maintains photomask layouts for photonic integrated circuits, performs quality control and mask review, develops automated layout tools and design rule checks, and collaborates with design, fabrication, and foundry teams.
About this role
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
How You Will Contribute:
Reporting to the manager of the Photonic Integrated Circuit (PIC) Design team, you will be primarily collaborating with the design team to create photomask layouts for our photonic chips. You will be a key link between device design and the semiconductor fabrication processes required to produce them, ensuring that the design can be realized within process constraints. This role requires good organizational skills and attention to detail. It offers the opportunity to learn how to develop and fabricate the advanced photonic components required for the optical networks of the future.
Responsibilities include:
- Generating and maintaining layout designs.
- Quality control and mask review.
- Developing automated layout tools, including design rule checks and scripting.
- Clear communication and collaboration with multidisciplinary Ciena teams and external foundry partners.
The Must Haves:
- BS degree or higher in a related engineering or science field (e.g. electrical engineering or material sciences)
- Experience (3+ years) with using a layout editor such as L-Edit, DW2000, or Cadence for semiconductor device layout.
- Experience in scripting masks and skilled in at least one programming language such as C/C++ or Python.
Assets:
- Familiar with semiconductor wafer fabrication methods (III-V, Si, etc.).
- Good understanding of semiconductor device physics and principles.
- Experience in design rule checking and other layout verification tools.
Pay Range
The annual pay range for this position is
Bachelors/Masters - $61,800 - $98,800
PHD - $74,200 - $118,600
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Skills
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