Physical Design Engineer

Physical Design Engineer

Axiado is building the future of AI powered digital infrastructure. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management. Our technology protects the world’s most critical infrastructure—from data centers to next generation cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems. 

Founded in 2019 and now over 150 employees are strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award. 

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world. 

If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey. 

We are looking for a motivated and hands-on Physical Design Engineer to join our ASIC team. The ideal candidate should have strong fundamentals in Physical Design and Timing Closure, a passion for solving implementation challenges, and a willingness to learn and grow in a fast-paced startup environment.

This role offers the opportunity to work across multiple aspects of backend implementation, including floorplanning, placement, CTS, routing, timing closure, power optimization, and physical signoff, while collaborating closely with experienced engineers across the ASIC development flow.

Key Responsibilities

Physical Design Implementation
• Participate in block-level and subsystem-level implementation from netlist to GDS.
• Perform floorplanning, placement, CTS, routing, and physical optimization activities.
• Analyze and resolve timing, congestion, utilization, and routing issues.
• Support ECO implementation and timing closure activities.

Timing Analysis & Closure
• Perform setup and hold timing analysis using PrimeTime or equivalent STA tools.
• Debug timing violations and work with design teams to identify and implement solutions.
• Analyze clock quality, timing margins, and constraint issues.

Physical Verification & Signoff
• Support DRC, LVS, ERC, Antenna, and density closure activities.
• Work with Calibre and/or ICV to analyze and resolve physical verification issues.
• Assist in signoff checks and tapeout readiness activities.

Power & PPA Optimization
• Analyze power, performance, and area tradeoffs.
• Support leakage reduction, clock optimization, and power recovery activities.
• Assist in implementing low-power design techniques and optimization strategies.

Automation & Productivity
• Develop and maintain Tcl/Python scripts to improve flow efficiency and automate repetitive tasks.
• Contribute to flow improvements and engineering productivity initiatives.

Collaboration
• Work closely with RTL, DFT, DV, and Physical Design teams to support successful project execution.
• Participate in design reviews and technical discussions.
 

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 2–5 years of ASIC Physical Design experience.
• Experience with at least one successful tapeout or advanced-stage implementation project.

Hands-On Experience In
• Floorplanning
• Placement and Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• ECO Implementation
• Physical Verification

EDA Tools
• Cadence Innovus
• Synopsys ICC2
• PrimeTime / Tempus
• Calibre / ICV

Scripting Skills
• Tcl scripting (required)
• Python scripting (preferred)

What We Are Looking For
• Strong hands-on Physical Design skills and solid backend fundamentals.
• Excellent debugging and problem-solving abilities.
• Curiosity to understand root causes rather than simply following existing flows.
• Willingness to take ownership of tasks and drive them to completion.
• Strong communication and teamwork skills.
• Ability to thrive in a fast-paced startup environment and adapt to evolving priorities.

Additional Information

All your information will be kept confidential according to EEO guidelines.