RTL Design Engineer

Client of FiniteHR, Startup

Our Client SeviTech is looking for RTL Design Engineer

About our Client: http://sevitechsystems.com/

Job Designation: RTL Design Engineer.

Job Location: Bangalore

Job Type: Permanent

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

• Prepare block/sub-system level timing constraints.

• Integrate IP/sub-system.

• Perform basic verification either in IP Verification environment or FPGA.

• B. Tech. or M. Tech. with 4 to 8 years of experience.

• Experience in Logic design / micro-architecture / RTL coding is a must.

• Expertise in Verilog is a must.

• Should have knowledge of AMBA protocols - AXI, AHB, APB.

• Experience in Synthesis / Understanding of timing concepts for ASIC or experience in Xilinx FPGA Design Implementation is required.

• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.

• Hands on experience in Multi Clock designs, Asynchronous interface is a must.

• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

• Knowledge of low power concepts and experience is a plus.

This is an Immediate Opportunity candidate with less than one month notice will be

preferred.

Please ignore this mail if the above profile doesn’t match with your current Job Role.

Thank you for your Valuable Time

Hoping for a Prompt Response!!!

Best regards,

Eswar-Recruiter

FiniteHR Consulting Pvt Ltd.

Additional Information

All your information will be kept confidential according to EEO guidelines.