Senior Principal FPGA & Digital Signals Processing Engineer

Lead the FPGA firmware architecture for Dragonfly, defining the optimal partitioning of signal processing across FPGA, GPU, and CPU to meet mission latency, throughput, and SWaP requirements.

Migrate GPU-based digital signal processing algorithms into efficient FPGA implementations, including floating-to-fixed point conversion, quantization analysis, word-length optimization, and bit-accurate verification.

Design reusable, portable FPGA IP that supports multiple AMD/Xilinx platforms including RFSoC, Versal, UltraScale+, and Zynq.

Develop real-time FPGA implementations for advanced RF signal processing including digital down conversion, filtering, FFTs, channelization, synchronization, demodulation, and protocol exploitation.

Implement and optimize wireless protocol processing for technologies such as Wi-Fi, Bluetooth/BLE, LoRa, LTE, and 5G NR.

Develop FPGA capabilities supporting direction finding (DF), beamforming, geolocation, and multi-channel phase-coherent signal processing.

Establish FPGA verification methodologies including simulation, automated regression testing, timing closure, hardware validation, and over-the-air testing.

Support hardware bring-up, integration, production validation, and field testing of Dragonfly systems.

Serve as the technical authority for FPGA firmware and DSP architecture, conducting design reviews, mentoring engineers, and establishing engineering best practices.

Contribute to product roadmap development, customer engagements, technical proposals, IRAD efforts, and emerging EW/SIGINT capability development.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; Master's or PhD preferred.

10+ years of FPGA development experience supporting RF, SDR, SIGINT, radar, wireless communications, or Electronic Warfare systems.

Demonstrated ownership of FPGA architecture from concept through deployed production systems.

Active Secret clearance required; ability to obtain or maintain TS/SCI preferred.

Expert proficiency with VHDL and/or SystemVerilog, RTL design, pipelining, finite state machines, clock domain crossing, and timing closure.

Extensive experience with AMD/Xilinx development tools including Vivado, Vitis, Vitis HLS, and RFSoC or Versal platforms.

Strong background in digital signal processing including FFTs, digital down/up conversion, FIR/IIR/CIC filters, multirate processing, fixed-point design, CORDIC, and AGC.

Experience implementing high-speed interfaces including AXI, PCIe, Ethernet, DDR memory, Aurora, and JESD204B/C.

Proficiency with MATLAB and/or Python for algorithm development and hardware verification, along with C/C++ development in Linux environments.

Experience with FPGA simulation, debugging, board bring-up, and RF laboratory validation using industry-standard tools.

Familiarity with Git, Agile development methodologies, and cross-functional hardware/software engineering teams.

Experience developing CUDA or GPU-based DSP algorithms and migrating them to FPGA implementations.

Experience implementing beamforming, direction finding, geolocation, MUSIC/ESPRIT, TDOA, or FDOA algorithms.

Knowledge of LTE, 5G NR, Wi-Fi, Bluetooth/BLE, LoRa, or other modern communications waveforms.

Experience with High-Level Synthesis (HLS), Simulink, MATLAB HDL Coder, or Model Composer.

Familiarity with RFNoC, GNU Radio, OpenCPI, SOSA, or CMOSS architectures.