SiC EPD Engineer

The Junior SiC EPD (Early Product Development) Engineer is a key technical role responsible for developing of new products on technologies within their development phase, identifying and addressing device and process weaknesses in early stages of manufacturing phase, advanced analysis and reduction of material and process related defects in SiC technologies, enabling high yield, cost competitiveness, and robust device performance for next-generation SiC power MOSFETs.
This position requires expertise in device physics, process integration, TCAD simulation, and yield engineering, with the ability to lead complex technical problem-solving activities across cross‑functional teams.

Qualifications

Required Qualifications

• Bachelor’s degree or higher in Engineering (Electrical Engineering, Materials Science, Physics, Semiconductor Engineering, or related field).
• Understanding semiconductor material science and device physics, including semiconductor fabrication and electrical characterization principles.
• Experience in SiC or HV Silicon device/process development, yield engineering, or defect analysis.
• Analytical and problem‑solving skills with the ability to independently drive complex technical issues.
• Strong communication skills in English, both written and verbal, for global collaboration.
• Ability to work with an open mindset, actively communicate, and effectively share technical information across teams.

Responsibilities

Key Responsibilities

• Plan, manage, and execute engineering lots and DOE activities, ensuring timely data generation and decision making.
• Perform yield analysis related to SiC material defects and fab‑induced defects, including epi‑related and process‑induced failures.
• Drive cost and yield analysis for SiC technologies, identifying major cost contributors and yield limiters.
• Provide technical support for production issues, including root‑cause analysis of yield and reliability excursions.
• Perform TCAD simulations to verify and optimize Silicon and SiC device technologies, including electrical performance and process sensitivity.
• Lead cost reduction and yield‑up initiatives through defect reduction, process optimization, and design/process co‑optimization.
• Conduct correlation analysis between PCM electrical data and in‑line process data to identify systematic issues and process sensitivities.
• Utilize layout tools (Cadence Virtuoso) to support device layout review, test structure definition, and design‑process interaction analysis.
• Collaborate closely with Device, Process, Yield, Reliability, Manufacturing, and external partners to ensure robust technology transfer and production sustainability.