SoC Design Verification Lead

Role Overview

We are looking for an experienced verification leader to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role leads system level verification. You will own the SoC verification plan and carry it through sign off and into tape out, covering boot and root of trust, clock and reset topology, low power behavior, and the IO and memory subsystems. You will set technical direction for a small team while staying hands on in the environment yourself.

Responsibilities

Own the SoC level verification strategy, plan and execution for the Velaura Physical AI SoC.

Build and lead a team of SoC verification engineers, setting technical direction and reviewing their work.

Define the SoC verification architecture and environment, and stay hands on in the code.

Coordinate verification across boot and security, clock and reset, low power, and the IO and memory subsystems.

Define sign off criteria and coverage goals, and drive closure through tape out.

Track and report verification progress, coverage and risk to engineering leadership.

Work with architecture, RTL, DFT, firmware and software teams on system level correctness and pre silicon bring up.

Partner with CAD and infrastructure teams on simulation, emulation and regression capacity.

Required Qualifications

12 or more years in design verification, including significant SoC level experience.

Experience leading SoC verification across multiple projects through sign off and tape out.

Experience building and leading a team of verification engineers.

Experience with SystemVerilog, UVM, C and C++ and coverage driven verification at system level.

Experience managing simulation flows on CPU based SoCs such as ARM or RISC-V.

Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6.

Experience verifying boot and root of trust, clock and reset topology, and low power behavior at system level, including CDC, RDC and UPF based flows.

Excellent communication skills and the ability to influence engineering leaders across disciplines.

Preferred Qualifications

Experience with HW and SW co verification and pre silicon software bring up.

Experience with emulation and FPGA prototyping at SoC level.

Experience with one or more of ISO 26262, IEC 61508, IEC 61511 or ISO 13849.

Experience verifying QoS, latency sensitive or real time systems.

Experience with post silicon bring up, debug and root cause analysis.

Experience building a verification team at an early stage company.

Familiarity with robotics, drones, autonomous vehicles or industrial automation systems.

Experience using AI assisted verification workflows to improve productivity and coverage.