Staff ML Accelerator Architect

Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.

In this role, you will report to a Hardware Engineering Manager.

You will:

• Analyze inference workloads and map them efficiently to hardware, proposing novel HW-friendly implementations and projecting performance
• Build scalable tools for performance modeling and evaluation of inference workloads
• Work closely with compiler and model developers to influence engineering tradeoffs and future model architectures
• Architect, simulate and design novel hardware solutions for state-of-the-art autonomous driving models
• Interact with cross-functional engineering teams to identify opportunities and realize architectural vision

You have:

• M.S. degree in Computer Science or Computer Engineering or equivalent practical experience
• 10+ years on designing/architecting complex, high performance architectures - CPUs, GPUs and/or ML accelerators - in the industry or through doctoral research
• 3+ years experience with machine learning architectures, acceleration and model optimization
• Deep knowledge of ML model architectures and their compute characteristics (bottlenecks, optimization opportunities)
• Strong programming and algorithmic problem solving skills

We prefer:

• Track record of analyzing workloads and architecting, delivering novel HW+SW solutions to vastly improve performance, efficiency for ML inference
• Proven ability leading cross-functional teams to deliver your architectural vision
• Familiarity with novel semiconductor technologies and their tradeoffs across the full hardware stack
• Experience with microarchitecture design (SystemVerilog or HLS)