Verification Lead for 4-Core Coherent System

You will lead the verification of our 4-core coherent AI system, through a team of 3–4 verification leads, all the way to tape-out sign-off.

About Semidynamics

Semidynamics builds memory-centric AI inference silicon in Barcelona. Our chips combine RISC-V CPUs, Vector and Tensor Units and our Gazzillion Misses™ memory engine, so that large language models are never starved of data. In April 2026, SK hynix, one of the world's leading memory makers, made a strategic investment in the company.

You will not inherit a mature flow at a company of 10,000 people. You will shape it, with a team you lead and a design team one desk away.

What you will do

Own the verification strategy for a 4-Core coherent system

• Write the verification plan: what is checked where, by whom, and how we know we are done.

• Set and track sign-off criteria for tape-out: functional and code coverage, bug trends, open risks.

• Decide where simulation, emulation and FPGA each give the best return, together with the respective team leads.

Lead the team

• Lead 3-4 block verification leads (covering L2 cache, interconnect, core and other components).

• Hire and grow the team: recruit engineers, mentor the leads, set clear goals.

• Make sure the team has healthy regressions and CI, and push automation.

• Be the verification voice in architecture and microarchitecture reviews, and report status clearly to project management.

Run the project

• Plan and estimate the verification effort, and keep the schedule realistic.

• Track tape-out risks and decide on mitigations early.

• Manage EDA licences and compute resources.

Why this role is different

• You own the verification strategy. The plan you write is the one the company tapes out with.

• You build the organisation. You shape the team, hire the people you want to work with, and choose methods and tools.

• A seat at the table. You review the architecture and microarchitecture with the design leads, early enough to change them.

• A hard, current problem. Verifying a memory-centric, coherent multi-core AI system is one of the most interesting challenges in the industry today.

What you bring

Must have

• 12+ years of hands-on design verification.

• Expert SystemVerilog and UVM: you have architected reusable, multi-agent environments.

• Proven technical leadership: you have defined a verification plan, driven coverage closure and guided other engineers.

• Experience managing people: you have led verification engineers or leads, and helped hire them.

• Hands-on experience verifying cache-coherent multi-core systems or subsystems.

• Experience with a major simulator and debugger (Questa, VCS or Xcelium; Visualizer or Verdi).

• Working knowledge of SoC bus protocols: AXI, CHI.

• B.Sc. or M.Sc. in Electrical or Computer Engineering, or equivalent experience.

• Fluent English.

Nice to have

• RISC-V, CPU cluster or AI accelerator verification.

• Scripting (Python, Bash) and experience running regression and CI infrastructure (GitLab).

• Formal verification.

• Emulation (Palladium, ZeBu or Veloce) and post-silicon debug.

• Strong integration verification: connectivity, reset and clock, interrupts, boot flow.

How you work

• You always ask: "Who/what actually checks this?"

• You keep inventing new scenarios to find the next bug before it finds us.

• You like to mentor, and you enjoy seeing engineers on your team grow.

Why Semidynamics

• Work at one of Europe's most promising deep-tech semiconductor scale-ups

• Accelerated development path, with room to grow into confidential computing, memory isolation and software security

• 4 days per week in the Barcelona office (city center), 1 day working from home

• 1 week of work from anywhere in the world

• Competitive package

• A collaborative, technical, growth-oriented environment that values direct ownership and clear thinking