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Posted 6 months ago

Design Verification EngineerTexas Instruments · Bengaluru

Design Verification Engineer

BengaluruOn-siteFull-time

AI Summary

Designs and builds UVM-based design verification environments, test plans and bus functional models for IP blocks in automotive UWB connectivity. Verifies RTL with constrained random and formal techniques.

About this role

IP Design Verification Engineer (2–5 Years Experience)

Are you passionate about Design Verification and excited about building next-generation automotive connectivity solutions?

Our team at Texas Instruments is expanding! We have been driving innovation in low-power BLE solutions, and now we are stepping into the exciting UWB (Ultra-Wideband) domain. If you want to work on cutting-edge IP development that powers real-world automotive applications, this is your opportunity.

Qualifications

Experience: 2–5 Years

Required Skillset:

  • Strong understanding of hardware description languages Verilog/ SystemVerilog / VHDL
  • Hands-on experience with UVM and building DV environments from scratch along with coding block functional models (BFM)
  • Test plan creation and execution
  • Solid understanding of fundamentals of CDC / RDC
  • Knowledge of constrained random verification techniques
  • Understanding of formal verification methodologies

Additional Advantage:

  • Experience in CPF / UPF low-power verification
  • Knowledge of AHB / APB bus protocols

Skills

AHBAPBBUS Functional ModelsCDCConstrained Random VerificationCPFFormal VerificationRDCSystemVerilogTest Plan CreationUPFUVMVerilogVHDL

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