Memory Layout

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟴𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟭𝟴𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟴-𝟭𝟴 𝗟𝗣𝗔)

Experience: 3+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for a skilled Memory Layout Engineer with hands-on experience in advanced semiconductor technology nodes to design and optimize high-performance memory layouts. This role is ideal for professionals with expertise in Memory Layout, TSMC 2nm & TSMC 3nm technologies, DRC, and LVS, along with a strong understanding of physical design methodologies and layout optimization.

As a Memory Layout Engineer, you will be responsible for developing accurate and manufacturable memory layouts while ensuring compliance with foundry design rules and quality standards. You will collaborate closely with circuit designers, physical design engineers, verification teams, and process engineers to deliver optimized memory macros that meet performance, power, and area (PPA) targets. This role offers the opportunity to work on cutting-edge process technologies and contribute to the development of next-generation semiconductor products.

Requirements

Key Responsibilities

• Design and develop high-quality memory layouts for advanced technology nodes, including TSMC 2nm and TSMC 3nm.
• Create optimized layouts for SRAM and other memory blocks while meeting performance, power, and area objectives.
• Perform layout verification using Design Rule Check (DRC), Layout Versus Schematic (LVS), and other physical verification tools.
• Identify and resolve layout-related issues, ensuring compliance with foundry design rules and manufacturing requirements.
• Collaborate with circuit design, physical design, and process teams to achieve optimal layout quality and functionality.
• Optimize layouts for signal integrity, reliability, electromigration, and manufacturability.
• Participate in layout reviews and implement feedback to improve design quality and efficiency.
• Support tape-out activities by ensuring layouts are verified, clean, and production-ready.
• Maintain documentation related to layout methodologies, verification results, and design guidelines.
• Continuously evaluate opportunities to improve layout methodologies, productivity, and design quality.

What Makes You a Great Fit

• 3+ years of experience in Memory Layout Engineering within the semiconductor industry.
• Strong hands-on experience with TSMC 2nm and/or TSMC 3nm process technologies.
• Solid expertise in Memory Layout, including SRAM and custom memory block layouts.
• Strong understanding of DRC, LVS, and physical verification methodologies.
• Experience working with industry-standard layout and physical verification EDA tools.
• Good understanding of semiconductor fabrication processes, layout constraints, and design-for-manufacturing (DFM) principles.
• Ability to optimize layouts for performance, power, area, and manufacturability.
• Strong analytical, debugging, and problem-solving skills with keen attention to detail.
• Excellent collaboration and communication skills, with the ability to work effectively in cross-functional engineering teams.
• Self-motivated mindset with the ability to manage multiple priorities and deliver high-quality results in a fast-paced development environment.