
Posted 24 days ago
Physical Design Engineer
AI Summary
Owns block-level and full-chip physical implementation from netlist to GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical verification for production silicon programs.
About this role
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll take designs from netlist to GDSII. You'll own floorplanning through closure on real silicon programs with leading semiconductor companies while helping Voltai's AI learn how expert physical designers make decisions.
What You’ll Do
Own block-level and full-chip physical implementation: floorplanning, placement, clock tree synthesis, and routing.
Drive timing, power, and congestion closure with synthesis and STA teams.
Close physical verification (DRC/LVS) and power integrity (IR drop, EM) for signoff.
Build and improve place-and-route flows and automation.
Evaluate AI-generated floorplans and implementation decisions, and help define what good looks like.
Work directly with customer teams on implementation challenges.
What We’re Looking For
5+ years of physical design experience with multiple production tapeouts.
Deep experience with Innovus or Fusion Compiler/ICC2.
Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
Experience at advanced nodes (7nm and below).
Strong Tcl and Python scripting.
Bonus Points
Full-chip integration or hierarchical design experience.
Experience with high-speed or low-power designs.
Interest in AI or machine learning applied to physical design.
Skills
Explore related jobs
More jobs at Voltai
Similar Clock Tree Synthesis jobs
- IRTL2PD Design Engineer (ASIC)Inabia Software & Consulting · Bay Area, California
- AAnalog Design Engineer- eInfochipsArrow Electronics, Inc. · Bangalore, India
- A
Principal/ Sr.Principal Digital Design EngineerAstera Labs · San Jose, California - A
Senior Director, Physical DesignAltera Semiconductor Technology Canada ULC · Regus, Madhapur - K
Analog Layout Engineer (Lead)Kandou Ai · Reading
Jobs in Palo Alto
- M
Administrative Support Team Associate, Stanford - Part TimeMacy's · Palo Alto, CA - M
Retail Sales Associate, Stanford Shopping Center - Full TimeMacy's · Palo Alto, CA - T
Sales EngineerTrail · Palo Alto Office - JAssistant Store ManagerJoe & the Juice / United States · Palo Alto, California
- ATechnical Program Manager (TPM)ALTEN Technology USA · Palo Alto, California
- N
Senior Cloud Network EngineerNubank · Palo Alto
Browse these categories
Market data for this role
All reports →- SeriesRole reportsOne role family at a time: how many openings, what changed this week, who is hiring, what it pays.
- SeriesSalary reportsWhat employers publish in job postings, by level and workplace. Not self-reported pay.
- Market overviewState of tech hiring, September 2026: up 4.8%Tech hiring rose 4.8% month over month in September 2026, with 411,122 new listings. Customer support and account executive roles led the growth.