Senior Foundry Integration Engineer

Own engineering tape-ins from finalized layout through successful release to external foundry partners.

Coordinate cross-functional tape-in readiness across Design, Layout, MEMS Integration, and Process Engineering teams.

Participate in tape-in quality reviews, ensuring layouts, documentation, and process assumptions are complete before release.

Track engineering lots from tape-in through wafer delivery and communicate status across the organization.

Define, coordinate, and track engineering split lots to maximize technical learning while optimizing wafer utilization.

Develop and manage short-loop experiments and Design of Experiments (DOEs) to investigate process issues and accelerate development.

Own NPI split management, including technical definition, schedule tracking, wafer tracking, engineering data collection, and results summarization.

Coordinate development activities with foundry engineers to ensure engineering objectives and timelines are achieved.

Review process flows alongside layout prior to tape-in to identify potential manufacturability or integration risks.

Evaluate process assumptions, mask layers, and layout interactions before fabrication.

Work closely with MEMS Integration Engineers to ensure process flows support device requirements.

Help identify opportunities to improve process robustness before engineering wafers are fabricated.

Perform process flow evaluations using layout review tools such as KLayout.

Analyze layout layers and process interactions to identify potential fabrication issues before tape-in.

Support simulation of process flow alternatives to improve manufacturability and development efficiency.

Grow into ownership of process flow modeling and simulation capabilities as the foundry development program expands.

BS, MS, or PhD in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, Chemical Engineering, or related discipline.

7+ years of experience working with semiconductor process development or process integration.

7+ years of experience collaborating with semiconductor foundries or external manufacturing partners.

MEMS or silicon photonics manufacturing experience.

Understanding of semiconductor fabrication process flows.

Experience defining or supporting Design of Experiments (DOE) activities.

Strong organizational skills with the ability to manage multiple parallel engineering activities.

Excellent written and verbal communication skills.

Experience supporting tape-ins or engineering wafer programs.

Familiarity with semiconductor layouts and mask data.

Experience reviewing process flows for manufacturability.

Knowledge of KLayout or similar layout visualization tools.

Experience with process simulation or process flow modeling.

Familiarity with commercial semiconductor foundries.

Professional proficiency in Mandarin Chinese is a plus to support technical collaboration with overseas foundry partners.