SoC Verification Engineer
San JoseOn-siteContract
AI Summary
A SoC Verification Engineer designs and executes verification plans for system-on-chip projects, focusing on USB, PCIe, or Ethernet interfaces using UVM/OVM/VMM methodologies.
About this role
SoC Verification Engineer
Title: SoC Verification
Location: San Jose, CA
Duration: 6-12 Months
Candidates must haveeither in USB or PCIe or Ethernet.
Job Details:
·Candidate must have 7+ years of experience in Verification
.· Must have experience in Verification methodology likeUVM, OVM, VMM(any one workable).
·Must have very good experience either in USB or PCIe or Ethernet.
·Must have experience inSystem Verilog.
- Understanding of ONFI, NVMe and SERDES a major plus.
Qualifications
Candidate must have 7+ years of experience in Verification
.
· Must have experience in Verification methodology likeUVM, OVM, VMM(any one workable).
·Must have very good experience either in USB or PCIe or Ethernet.
·Must have experience inSystem Verilog.
- Understanding of ONFI, NVMe and SERDES a major plus.
Additional Information
Anvesh Reddy
609 269 2719
Skills
EthernetOVMPCIeSerdesSystem VerilogUSBUVMVMM
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