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Posted 9 days ago

Lead Design Engineer

BeijingOn-siteFull-time

AI Summary

Lead Design Engineer at Cadence performs physical design implementation including floor planning, place and route, clock tree synthesis, timing closure, and physical verification for low-power and high-speed designs, and leads next-generation PHY IP physical design methodology and flow development.

About this role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
  • The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.

We’re doing work that matters. Help us solve what others can’t.

Skills

Antenna CheckClock Tree SynthesisDFM ClosureDRCEM/IR SignoffFloor PlanningHigh-speed DesignLow-power DesignLVSPHY IPPhysical DesignPhysical VerificationPlace And RoutePower Integrity SignoffSignal Integrity SignoffTiming Closure

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