Posted 1 month ago
Principal Physical Verification EngineerNXP Semiconductors France SAS · Bengaluru
Principal Physical Verification Engineer
BengaluruOn-siteFull-time
AI Summary
Performs full-chip and block-level physical verification signoff for VLSI designs, ensuring compliance with foundry and reliability requirements through DRC, LVS, ERC, and antenna/density checks.
About this role
We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.
Key Responsibilities
- Perform physical verification (PV) for block-level and full-chip designs, including:
- Design Rule Check (DRC)
- Layout Versus Schematic (LVS)
- Electrical Rule Check (ERC)
- Antenna, density, and reliability checks
- Drive signoff closure by identifying and resolving PV violations efficiently.
- Work with physical design and layout teams to debug and fix violations.
- Develop and maintain runsets, decks, and automation flows using industry-standard tools.
- Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
- Lead tapeout readiness reviews and ensure high-quality database delivery.
- Perform hierarchical verification and regression management.
- Participate in improving verification methodologies, runtime, and capacity optimization.
- Interface with foundry and EDA vendors to resolve tool or deck-related issues.
- Mentor junior engineers and review their work as needed.
Preferred / Added Advantage Skills
- Exposure to Physical Design (PD) concepts, including:
- Floorplanning (macro placement, block shaping, congestion awareness)
- Power Delivery Network (PDN) design (power grid, IR drop considerations)
- Understanding of:
- Placement, CTS, routing flows
- PD-PV interaction and impact of layout decisions on DRC/LVS closure
- Knowledge of:
- EM/IR, latch-up, ESD reliability checks
- Multi-patterning / EUV constraints
- Experience with full-chip integration and SoC-level challenges
- Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
- Exposure to flow automation and methodology development
Soft Skills
- Strong analytical and problem-solving ability
- Effective communication across cross-functional teams
- Ownership mindset with focus on quality and timelines
- Ability to work independently and guide team members
Skills
Antenna ChecksCTSDensity ChecksDesign Rule Check (DRC)EDA ToolsElectrical Rule Check (ERC)EM/IRESD ReliabilityEUV ConstraintsFloorplanningFlow AutomationFoundry Deck AnalysisHierarchical VerificationIR Drop AnalysisLatch-upLayout Versus Schematic (LVS)Multi-patterningPDK AnalysisPlacementPower Delivery Network (PDN)Regression ManagementReliability ChecksRouting FlowsRunset DevelopmentSoC IntegrationTapeout Readiness
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