Research Engineer - Mid-Training
AI Summary
Mid-level to senior Research Engineer focusing on training frontier models for semiconductor design and verification, including data generation, distillation, continual learning, and scaling across GPUs.
About this role
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
Mid Training
You will train frontier models to become highly knowledgeable semiconductor design and verification experts that serve as the foundation for reinforcement learning and automated chip development. You will develop methods for generating and curating synthetic design data, performing model distillation, and enabling continual learning at scale. You will work closely with hardware engineers, RL researchers, and verification specialists to create evals that guide design data quality and model improvement. You will collaborate with compute engineers to scale efficient training across thousands of GPUs and RL environments. You will build high-performance tools to investigate how data and simulation shape model-driven design intelligence.
You might thrive in this role if you have experience with
Training LLMs or foundation models on semiconductor design and verification corpora (e.g., RTL, netlists, PDKs, simulation logs)
Modeling design scaling laws and optimizing compute budgets for chip-design-specific workloads
Generating large-scale synthetic design data (e.g., RTL variants, testbenches, verification traces)
Building evals that correlate with downstream design metrics (e.g., timing closure, power, area, verification coverage)
