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Omni Design Technologies

Posted 4 months ago

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Physical Design Lead/Manager

HyderabadHybridFull-time

AI Summary

Leads and manages the physical design of next-generation mixed-signal SoCs for automotive and space applications, driving implementation of high-speed ADC/DAC and high-speed interfaces end-to-end.

About this role

Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers.

Omni Design is developing exciting high-speed Mixed-Signal SOC. We are looking for a Lead/Manager of Physical Design to make these high performance Mixed-Signal SOCs a reality

Role and Responsibility

  • Own and drive the physical implementation of next-generation Mixed-Signal SOC with HS ADC/DAC, HS interfaces like PCIe, LPDDR, MIPI, USB2/3, Gig Ethernet etc.
  • Understand the requirements and define physical implementation methodologies.
  • Collaborate with architecture, design, front end and CAD teams to deliver high-quality physical designs.
  • Implement and verify designs at all levels of hierarchy in the SOC.
  • Interact with foundry over matters of technology, schedule, and signoff

    • Qualifications and Experience

  • BSEE Required, MSEE Preferred
  • 8+ years of experience of physical design in SOCs.
  • 3+ years of experience in managing projects and leading teams.
  • Hands-on expertise in all of the following areas: Floorplanning, Power planning, Implementation of UPF Methodology, Logic and clock tree synthesis, Placement , Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
  • Full chip/ top-level expertise in multiple chip tape-outs.
  • Good understanding and experience in SCAN, BIST, and ATPG.
  • Strong background in TCL/Perl/Python programming is a must.
  • Expertise in double patterning process nodes is desirable. Experience with sub 40 nM nodes required
  • Expertise in Cadence or Synopsys RTL-to-GDSII flow is preferred.

    • Expectations

  • Do the FC Floor Plan and Layout
  • Set up the EDA tools and develop the scripts
  • Develop the UPF methodology
  • Implement the Power, Clock Grid
  • Generate the SDF files
  • Do the DRC, ERC, LVS, SI and Cross talk checks, Do the DFM checks
  • Tapeout the chip
  • Manage and mentor the PD and custom layout team
  • Make changes, as needed to the custom layout of the IP
  • Release the GDS2 to the Fabs

    • Skills

    CadenceClock Tree SynthesisCross-talk AnalysisDRCEM IR AnalysisFloorplanningLVSPerlPhysical VerificationPlacementPythonRoutingSynopsysTCLTiming ClosureUPF

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